Logic gates come from transistor networks that pull an output high or low under specific input conditions.
NAND and NOR are especially important because they can be used to build other logic.
Pull-Down Networks
The NMOS network controls when the output can be pulled down to ground.
Two NMOS transistors in series require both to be on before there is a path to ground.
That creates an “all inputs high” condition for pull-down.
flowchart TD out["Output"] --> n1["NMOS A"] n1 --> n2["NMOS B"] n2 --> gnd["Ground"]
If both inputs are high, both NMOS devices conduct, and the output can be pulled low.
Pull-Up Networks
The PMOS network provides the complementary pull-up behavior.
For a NAND gate, PMOS devices are arranged so the output is pulled high unless both inputs make the pull-down path win.
The result is:
| A | B | NAND Output |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
NOR
For NOR, the arrangement changes.
The output is high only when both inputs are low. If either input is high, an NMOS path can pull the output low.
| A | B | NOR Output |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
Boundary
The truth table is a summary of circuit behavior, not the source of the behavior.
The durable model is:
A CMOS gate implements a logical rule by arranging PMOS pull-up and NMOS pull-down networks so each input combination drives the output into the intended voltage range.